Integrated circuits (ICs) are typically formed on a semiconductor wafer that is subsequently cut into individual dies. The dies are then typically encased in a package, with various elements on the die connected to corresponding leads on the package. In conventional ICs, each die can include numerous individual devices, including transistors, diodes, capacitors, resistors, and inductors. Moreover, each die can include various connections between such devices, including multiple levels of wiring and various types of vertical interconnects.
A potential problem with such conventional ICs is a formation of cracks on the die. Cracks can form on dies with a variety of structures, including fissures, fractures, and/or other dislocations. The cracking of dies during fabrication, cutting, assembly, packaging, and/or operation can result in various types of IC failures.
The assembly process of semiconductor dies in package or modules involves mechanical forces on the electrical contact pads to connect to a lead frame by solder or bonding process. The mechanical forces create local stress on the pad surfaces and could result mechanical cracks near or below the pad contact surface. Mechanical forces on the carrier tapes used to feed chip scale packaged units with ball or pillar solder pads could create cracks even before the assembly process. Since the cracks can grow after every thermal or mechanical stress of the assembled device sometimes affected devices cannot be revealed during final test and the units may fail in the field.
Die cracks can lead to runaway current leakage that may render the IC inoperable. Furthermore, as modern dies become smaller, thinner, and more densely populated with integrated electrical devices, they can become more susceptible to cracks and resulting IC failures. It is desired to improve the detectability of cracks.